1. Field of the Invention
The present invention generally relates to high-performance interconnection of multiple communicating processing systems. More specifically, the present invention is suitable for Very Large Scale Integration (VLSI) Integrated Circuit (IC) implementation.
2. Description of the Related Art
High-quality, networked multimedia consumer electronics devices require concurrent operation of multiple processing systems. Examples devices are high-resolution networked video Digital Versatile Disk (DVD) recorder, player, set top box and satellite receivers. The functional capability, performance, cost and power consumption of a multimedia consumer electronics device is greatly affected by the choice of the interconnection mechanism. Power and cost efficient implementations require special considerations for application and algorithmic requirements, such as access latency, bandwidth, and number of concurrent traffic streams. With the increasing complexity of the VLSI ICs, efficient operation as measured by increased utilization of internal resources, support for multiple functions, and power consumption efficiency become increasingly more important yet complex.
In many current design practices, various processing units are joined together using one or several shared interconnect bus. Example on-chip shared bus mechanisms are Advanced High-performance Bus (AHB), Peripheral Component Interface (PCI) or other similar proprietary mechanisms. Parallel shared interconnect bus mechanisms are attractive due to design, validation, manufacturing, testing simplicity, and high transfer rate but suboptimal due to power consumption, scalability to large number of units, timing skews, and operational speed. Multiple shared hierarchical parallel interconnects such as multi-layer AHB or PCI, are an attractive alternative due to potential for localization and organization of data traffic but incur additional cost, power consumption, validation, and design complexity. Recently, Network-on-Chip (NOC) interconnects have been proposed and demonstrated by some researchers as an alternative suitable for VLSI IC implementation. While NOC address many deficiencies of the shared parallel interconnect bus (e.g. scalability to large number of devices, timing skew and operational speed), they do not provide fine grain optimization mechanisms for application and algorithm specific communication traffic. Switching fabric interconnect technologies are viable alternatives; however most are proprietary and not well suited for interconnection of on-chip system units.
Efficient concurrent system operation requires simultaneous support of many communicating traffic sources and destinations. For example, in a digital video decode system, there are several operational modes such as motion compensation, inverse transform, inverse quantization and video post processing. Each mode has unique processing resource requirements depending on factors such as algorithmic complexity, available processing resource capability, communication resources and real-time deadlines. Each operational mode is characterized by data and control information traffic transfer between one or several source and destination units. The performance and power consumption efficiency of the overall system can be significantly improved by ensuring the interconnection is optimized for each or arbitrary plurality of modes.
Currently, none of the reported, VLSI implementation suitable, interconnect mechanisms provide facilities for fine grain interconnect configuration and optimization based on system application modes or algorithms. It can thus be appreciated that a need exists for novel, cost, and power efficient, VLSI implementation suitable, and dynamically reconfigurable interconnection mechanism that can be optimized to meet fine-grained application and algorithmic requirements.